`include "cpu_def.vh"

module decode_branch(
  input [31:0] instr,
  input [31:0] pc   ,

  output [31:0] br_target,
  output [31:0] jp_target
);

  wire [31:0] simm = {{14{instr[15]}}, instr[`INSTR_IMM], 2'b00};
  wire [31:0] pc_seq = pc + 4;
  
  assign br_target = pc_seq + simm;
  assign jp_target = {pc_seq[31:28], instr[`INSTR_INDEX], 2'b00};

endmodule
